This invention relates to a communications systems interface and more particularly to a memory circuit and command protocol for use therewith in a communications system.
Heretofore, data processing systems, and particularly calculator systems, utilized clock synchronized machine states comprising an instruction cycle, with three defined signal types (command, address, data, control) being transferred between parts of the system on a bus during respective predefined machine state intervals of each instruction cycle. Each instruction cycle was of identical length (equal time intervals), with all predefined machine states cycling irrespective of whether the associated (respective) predefined signal type corresponding to that machine state was to be transferred during the instruction cycle. Furthermore, each instruction cycle corresponded to a single command cycle. Furthermore, separate buses, serial or parallel, were used for transferring different types of signals to different areas wthin the data processing system.